Relay.h

00001 #ifndef RELAY_H
00002 #define RELAY_H
00003 
00004 #include <GNU_defs.h>
00005 #include <arch/param.h>
00006 
00007 /*Relay.h
00008 */
00009 
00018 #define PORT2PMASK 0x3f
00019 #define PORT2PHMASK 0xc0
00020 #define PORT2HMASK 0x0c
00021 
00022 
00023 #define PORT0_IN  PORTA     
00024 #define PORT1_IN  PTIT
00025 #define PORT2_IN  ((PTIP&PORT2PMASK)|((PTIH&PORT2HMASK)<<4))
00026 
00027 
00028 #define PORT0_OUT(out) {PORTA = out;}
00029 #define PORT1_OUT(out) {PTT = out;}
00030 #define PORT2_OUT(data) {PTP=(data&PORT2PMASK+(PTP&PORT2PHMASK));PTH=PTH&(~PORT2HMASK) + ((data&PORT2PHMASK)>>4);}
00031 
00032 
00033 #define PORT0CFG_IN DDRA
00034 #define PORT1CFG_IN DDRT
00035 #define PORT2CFG_IN ((DDRP&PORT2PMASK)|((DDRH&PORT2HMASK)<<4))
00036 
00037 #define PORT0CFG_OUT(out) {DDRA = out;}
00038 #define PORT1CFG_OUT(out) {DDRT = out;}
00039 #define PORT2CFG_OUT(data) {DDRP=(data&PORT2PMASK+(DDRP&PORT2PHMASK));DDRH=DDRH&(~PORT2HMASK) + ((data&PORT2PHMASK)>>4);}
00040 
00041 #define PLDADD_PORT PTJ
00042 #define PLDWR_PORT  PTJ
00043 
00044 
00045 
00046 
00047 
00048 
00049 
00050 #define PLD_CS_PORT PTJ
00051 #define PLD_DATA    PORTB
00052 #define PLD_DDR     DDRB 
00053 #define PORT3PORT   PORTE
00054 #define PORT3CFGPORT DDRE
00055 #define PORT3MASK   0x1F
00056 
00057 
00058 #define ADD_BIT     1
00059 #define WRITE_PIN   2
00060 #define CS_PINMASK  0x80
00061 
00062 #define PLD_DDR_IN() PLD_DDR=0
00063 #define PLD_DDR_OUT() PLD_DDR=0xff
00064 #define PLD_ADDRESS(address) {PLDADD_PORT=(address&ADD_BIT)|(PLDADD_PORT&(~ADD_BIT));}
00065 #define PLD_WRITEMODE() (PLDWR_PORT&=~WRITE_PIN)
00066 #define PLD_READMODE() (PLDWR_PORT|=WRITE_PIN)
00067 #define PLD_CS_ON() (PLD_CS_PORT&=~CS_PINMASK)
00068 #define PLD_CS_OFF() (PLD_CS_PORT|=CS_PINMASK)
00069 #define PLD_INIT() {DDRJ|=(ADD_BIT|WRITE_PIN|CS_PINMASK);PLD_DDR_IN();PLD_CS_OFF();}
00070 
00071 #define PLD_WRITE(address,data) {PLD_DDR_OUT();PLD_ADDRESS(address);PLD_DATA=data;PLD_WRITEMODE();PLD_CS_ON();PLD_READMODE();PLD_CS_OFF();}
00072 #define PLD_READ(address)
00073 
00074 
00075 #ifdef REV2PLD
00076 #define PORT3_OUT(data) {PLD_WRITE(1,data);PORT3PORT=(data&PORT3MASK)|(PORT3PORT&(~PORT3MASK));}
00077 #define PORT4_OUT(data) {PLD_WRITE(0,data);}
00078 #define PORT5_OUT(data)
00079 
00080 #ifdef MODBUSCODE
00081 #define PORT3_IN (PORT3PORT&PORT3MASK)|(CopData.Holding[3]&(~PORT3MASK))
00082 #define PORT4_IN CopData.Holding[4]
00083 #else
00084 #define PORT3_IN ((PORT3PORT&PORT3MASK)&(~PORT3MASK))
00085 #define PORT4_IN 0
00086 #endif
00087 #define PORT5_IN PLD_read_port(2)
00088 
00089 #define PORT3CFG_OUT(data) {PORT3CFGPORT = (data&PORT3MASK)|(PORT3CFGPORT&(~PORT3MASK));}
00090 #define PORT4CFG_OUT(data)
00091 #define PORT5CFG_OUT(data)
00092 
00093 
00094 #define PORT3CFG_IN (((PORT3CFGPORT&PORT3MASK)|(~PORT3MASK))&0xfc)
00095 #define PORT4CFG_IN 0xff
00096 
00097 #define PORT5CFG_IN 0
00098 
00099 #else  //rev 3 PLD
00100 #define PORT3_OUT(data)  //this is input only now
00101 #define PORT4_OUT(data) {PLD_WRITE(0,data);Holding[0] = data;} //added holding register
00102 #define PORT5_OUT(data) {PLD_WRITE(1,data);Holding[1] = data;}//PLD address 1 is now byte wide port 5
00103 
00104 #define PORT3_IN (PORT3PORT&PORT3MASK)|(PLD_read_port(1)&(~PORT3MASK))//all readable now, PLD at address 1
00105 #define PORT4_IN Holding[0]//no change
00106 #define PORT5_IN Holding[1]//write only now
00107 
00108 #define PORT3CFG_OUT(data) //none of these ports are configurable
00109 #define PORT4CFG_OUT(data)
00110 #define PORT5CFG_OUT(data)
00111 
00112 
00113 #define PORT3CFG_IN 0
00114 #define PORT4CFG_IN 0xff
00115 #define PORT5CFG_IN 0xff
00116 #endif
00117 
00118 
00119 
00122 #define STATUS_ON()     (STATUS_PORT|=STATUS_MASK)
00123 #define STATUS_OFF()    (STATUS_PORT&=~STATUS_MASK)
00124 
00125 
00135 int __attribute__((far))port_cfg(unsigned int channel, u8 data);
00136 
00137 
00150 int __attribute__((far))Digital_out(u8 data,unsigned int channel);
00151 
00152 
00162 u8 __attribute__((far))PLD_read_port(int port);
00163 
00164 
00174 u8 __attribute__((far))read_port_cfg(unsigned int channel);
00175 
00176 
00187 u8 __attribute__((far))Digital_in(unsigned int channel);
00188 
00199 int __attribute__((far))Digital_Mask_Write(int data,u8 mask);
00200 
00210 int __attribute__((far))Digital_Mask_Cfg(int cfg,u8 mask);
00211 
00219 int __attribute__((far))Init_PLD_Holding(void);
00220 
00222 #endif

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